Configuration of programmable logic devices with routing core generators

ABSTRACT

A system and method for configuration of a programmable logic device using routing cores. A program executing on a processor includes instructions that select functions to be provided by the programmable logic device. The instructions invoke functions from a library of logic and router core generators to define logic cores and router cores to intercouple the logic cores. From the logic and router core definitions, the program utilizes a bit-stream library to generate programming bits. The programmable logic device is then loaded with the programming bits by the program.

RELATED PATENT APPLICATIONS

This patent application is a continuation-in-part of U.S. patentapplication Ser. No. 08/919,531 entitled, “METHOD OF DESIGNING FPGAS FORDYNAMICALLY RECONFIGURABLE COMPUTING,” filed on Aug. 28, 1997 by StevenA. Guccione now U.S. Pat. No. 6,078,736.

This application is also related to the following two commonly ownedpending applications:

1. U.S. patent application Ser. No. 09/023,334 entitled “NETWORKCONFIGURATION OF PROGRAMMABLE CIRCUITS”, filed Feb. 13, 1998 by StevenA. Guccione; and

2. U.S. patent application Ser. No. 09/049,891 entitled“CONTEXT-SENSITIVE SELF IMPLEMENTING MODULES” filed Feb. 27, 1998 byEric F. Dellinger, James L. Hwang, Sujoy Mitra, Sundararajarao Mohan,and Ralph D. Wittig.

The contents of the above applications are incorporated herein byreference.

COPYRIGHT NOTICE

A portion of the disclosure of this patent document contains materialthat is subject to copyright protection. The copyright owner has noobjection to the facsimile reproduction by anyone of the patent documentor the patent disclosure, as it appears in the Patent and Trademarkoffice patent file or records, but otherwise reserves all copyrightrights whatsoever.

FIELD OF THE INVENTION

The present invention generally relates to configuration of programmablelogic devices, and more particularly, to run-time reconfiguration ofprogrammable logic devices.

BACKGROUND OF THE INVENTION

Field programmable gate arrays (FPGAs), first introduced by XILINX in1985, are becoming increasingly popular devices for use in electronicssystems. In general, the use of FPGAs continues to grow at a rapid ratebecause FPGAs permit relatively short design cycles, reduce coststhrough logic consolidation, and offer flexibility in theirreprogrammability. The capabilities of and specifications for XILINXFPGAs are set forth in “The Programmable Logic Data Book,” published in1998 by XILINX, Inc., the contents of which are incorporated herein byreference.

The field of reconfigurable computing has advanced steadily for the pastdecade, using FPGAs as the basis for high-performance reconfigurablesystems. Run-Time Reconfigurable (RTR) systems distinguish themselves byperforming circuit logic and routing customization at run-time. RTRsystems using FPGAs are expected to result in systems that require lesshardware, less software, and fewer input/output resources thantraditional FPGA-based systems. However, scarcity of software thatsupports RTR is believed to be one reason that RTR has been outpaced byresearch in other areas of reconfigurable computing.

Whereas with traditional configuration of FPGAs the time taken togenerate a programming bitstream is generally not real-time critical,with RTR systems, the time required to generate the programmingbitstream may be critical from the viewpoint of a user who is waitingfor the FPGA to be reconfigured. Thus, it may be acceptable to takehours to generate a programming bitstream using traditionalconfiguration methods. In a run-time environment, however, it isexpected that the reconfiguration process require no more than a fewseconds or even a fraction of a second.

Reconfiguration of an FPGA may include reparameterizing various logiccores and rerouting connections between the logic cores. Parameterizablecores permit the user to enter information about the desired core, fromwhich a customized circuit conforming to this information isconstructed. An example of a parameterizable core is an adder core toproduce an adder circuit. Example parameters include the size, forexample, 4 bit, 8 bit, or 16 bit, and serial versus parallel.

Once reparameterized, the connections between cores and placement on theFPGA must be established. Routers in a traditional configuration processgenerally route connections for all the circuit elements. That is, theserouters define connections for all the circuit elements in a design.Therefore, in an RTR environment, traditional reparameterization androuting methods are inappropriate given the real-time operatingconstraints.

A system and method that address the aforementioned problems, as well asother related problems, are therefore desirable.

SUMMARY OF THE INVENTION

In various embodiments, the invention comprises methods and systems forconfiguration and run-time reconfiguration of programmable logic devicesusing routing cores. In one embodiment, a method is provided forconfiguration of a programmable logic device, where the programmablelogic device is coupled to a processor. A library that comprises logiccore generators and one or more router core generators is used forconfiguration, and the method comprises executing a program on theprocessor, the program including instructions that select functions tobe provided by the programmable logic device. One or more of the logiccore generators, in response to the program, generate logic coredefinitions that define at least two logic cores; and the routergenerators, in response to the program, generate at least one routercore definition that defines a coupling of the logic cores in theprogrammable logic device. From the logic and router core definitions,programming bits are generated and the programmable logic device is thenloaded with the programming bits.

In another embodiment, a system for run-time reconfiguration of aprogrammable logic device is provided. The system comprises a processorarranged to host a program, where the program includes instructions thatselect functions to be provided by the programmable logic device. Alibrary of logic core generators and router core generators isaccessible to the application program and executable on the processor;and a programming bit generator is accessible to the application programfor generation of programming bits in response to output of the logiccore and router core generators. A programmable logic device is coupledto the processor and configurable with the programming bits.

An apparatus for configuration of a programmable logic device that iscoupled to a processor is provided in another embodiment. The apparatuscomprises: means for selecting functions to be provided by theprogrammable logic device with program instruction references to alibrary of logic core and router core generators; means for generatinglogic core definitions; means for generating router core definitionsthat define couplings between the logic cores in the programmable logicdevice; means for generating programming bits from the logic coredefinitions and router core definition; and means for loading theprogrammable logic device with the programming bits.

The above summary of the present invention is not intended to describeeach disclosed embodiment of the present invention. The figures anddetailed description that follow provide additional example embodimentsand aspects of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

Various aspects and advantages of the invention will become apparentupon review of the following detailed description and upon reference tothe drawings in which:

FIG. 1 is a bloc diagram that illustrates a prior art design flow;

FIG. 2 is a block diagram of system for configuration of a programmablelogic device, according to an example embodiment of the invention;

FIG. 3 is a flowchart of a process for initial configuration andrun-time reconfiguration of a programmable logic device according to anexample embodiment of the invention; and

FIG. 4 is a schematic that illustrates a portion of an example FPGAconfigured in accordance with example program code fragments set forthin the description.

While the invention is susceptible to various modifications andalternative forms, specific embodiments thereof have been shown by wayof example in the drawings and will herein be described in detail. Itshould be understood, however, that the detailed description is notintended to limit the invention to the particular forms disclosed. Onthe contrary, the intention is to cover all modifications, equivalents,and alternatives falling within the spirit and scope of the invention asdefined by the appended claims.

DETAILED DESCRIPTION

The present invention is believed to be applicable to a variety ofconfigurable electronic systems. Such configurable electronic systemsinclude, for example, mobile telephones, set-top boxes, computer systemsand others as will be recognized by those skilled in the art. Thepresent invention has been found to be particularly applicable andbeneficial in electronic systems having programmable logic devices, forexample, field programmable gate arrays (FPGAs). While the presentinvention is not so limited, an appreciation of the present invention ispresented by way of a particular example application, in this instance,in the context of an example electronic system that includes a processorcoupled to an FPGA.

Design of a circuit implemented in an FPGA using a reconfigurable logiccoprocessor currently requires a combination of two distinct designpaths, as shown in FIG. 1. The first and perhaps most significantportion of the effort involves circuit design using traditional CADtools. The design path for these CAD tools typically comprises enteringa design 101 using a schematic editor or hardware description language(HDL), using a netlister 102 to generate a net list 103 for the design,importing this netlist into an FPGA map, place, and route tool 104,which finally generates a bitstream file 105 of configuration data usedto configure the FPGA 106.

Once the configuration data has been produced, the next task is toprovide software to interface the processor to the FPGA. The user entersuser code 107 describing the user interface instructions, which is thencompiled using compiler 108 to produce executable code 109. Theinstructions in executable code 109 are then used by the processor tocommunicate with the configured FPGA 106. It is also known to useexecutable code 109 to control the configuration of FPGA 106 withbitstream file 105. This series of tasks is usually completely decoupledfrom the task of designing the circuit and hence can be difficult anderror-prone.

In addition to the problems of interfacing the hardware and software inthis environment, there is also the problem of design cycle time. Anychange to the circuit design requires a complete pass through thehardware design tool chain (101-106 in FIG. 1). This process time istime consuming, with the place and route portion of the chain typicallytaking several hours to complete.

Finally, this approach provides no support for run-time reconfiguration.The traditional hardware design tools provide support almost exclusivelyfor static design. It is difficult to imagine constructs to supportrun-time reconfiguration in environments based on schematic or HDLdesign entry.

FIG. 2 is a block diagram of a system 200 for configuration of aprogrammable logic device 202, according to an example embodiment of theinvention. It will be appreciated that the system 200 of FIG. 2 alsosupports run-time reconfiguration of the programmable logic device 202.

The system 200 includes a user application program 204 that is writtenin, for example, the Java® language. The application program 204 may bewritten to perform various functions relative to the environment inwhich the system 200 is used. For example, in addition to configurationand/or run-time reconfiguration of the programmable logic device 202,the user application program 204 may be programmed to provideuser-interface functions and/or digital signal processing.

The core library 206 is a collection of macrocell or “core” generatorsthat are implemented as Java classes. The cores are generallyparameterizable and relocatable within a device. Examples of coresinclude counters, adders, multipliers, constant adders, constantmultipliers, flip-flops and other standard logic and computationfunctions.

Application program interface 207 and bit-level interface 208 allow userapplication program 204 to write programming bits 210 to storage device212. Application program interface 207 responds to high level commandsfrom user application program 204 to implement desired functions inportions of programmable logic device 202. For example, user applicationprogram 204 might instruct application program interface 207 toimplement an AND gate in logic block 3,4 of programmable logic device202. Bit-level interface 208 includes a set of lower level functions,one or more of which are invoked when the user application program 204references the application program interface 207. For example, inresponse to the command to implement an AND gate in block 3,4, bit-levelinterface 208 will write 0's and 1's to particular bits 210 of storagedevice 212. The set of functions in bit-level interface 208 manipulateselected ones of the programming bits 210, based on the type ofprogrammable logic device to be configured. For example, some of thefunctions in the set may be programmed for certain devices in theXC4000EX family of FPGAs from XILINX, and others of the functions mayprogrammed for other devices in the XC4000XL family. Bit-level interfacesoftware is generally understood by those skilled in the art. Forexample, bit-level interface software has been provided with the XC6200series FPGA from XILINX.

The programming bits are stored in a storage element 212. Storageelement 212 may be magnetic, optical, electronic, or a suitablecombination thereof that is readable and writable.

While the core library 206, user application 204, application programinterface 207, and bit-level interface 208 are written in Java in theexample embodiment, it will be appreciated that many other languageswould also be suitable.

Hardware interface 214 includes a portable layer of software andaccompanying hardware to couple the user application program 204 to aprogrammable logic device 202. For example, the hardware interface 214may be the Xilinx Hardware Interface (XHWIF) which is available fromXILINX.

The processor 216 is coupled to the programmable logic device 202 viathe hardware interface 214. The functional requirements of the system200 dictate the particular style and capabilities of the processor 216.For example, some applications may call for a RISC based processor whileothers may call for a CISC. Various ones of special purpose or generalpurpose processors from manufacturers such as Intel, Sun Microsystems,Motorola, IBM, AMD and others may be suitable.

FIG. 3 is a flowchart of a process for initial configuration andrun-time reconfiguration of a programmable logic device according to anexample embodiment of the invention. In accordance with an exampleembodiment of the invention, the process can be implemented as anapplication program, for example, user application program 204 of FIG.2. The example process proceeds in two example phases. In the firstphase, the programmable logic device is initially configured, and in thesecond phase, the device is dynamically reconfigured in accordance withapplication processing requirements.

At step 302 various components in the example system, aside from theprogrammable logic device, are initialized. The example process thenproceeds with configuration of the programmable logic device.

Selected functions provided by the core library 206 (FIG. 2) are invokedat step 304 to generate logic core definitions. The functions selectedare those required to generate one or more logic cores forimplementation on the programmable logic device. The functions areselected via execution of program instructions set forth in the exampleuser application program 204. Examples set forth later in thisspecification will provide instructions for the user application program204 and functions of the core library 206.

At step 306, selected functions of the core library are invoked togenerate router cores. The router cores provide the informationnecessary to connect selected ones of the logic cores when the logiccores are implemented in the programmable logic device 202. Furtherdetails are provided in the example code segments that follow and alsoin FIG. 4. In various embodiments, the router cores can, for example,utilize the direct, single, double, quad, long, and global signal linesprovided by the XC4000 family of FPGAs from XILINX.

Based on the generated logic cores and router cores, the applicationprogram interface 207 and bitstream interface 208 are invoked at step308 to generate programming bits to configure the programmable logicdevice 202. The initial configuration bitstream is downloaded to theprogrammable logic device 202 at step 310, and the programmable logicdevice is made an operational component of the example system 200 atstep 312.

Step 314 begins the run-time phase of processing by the applicationprogram 204. The example application program 204 includes code tomonitor various application conditions, as illustrated at step 316. Anexample application provides adaptive digital filtering, which dependson various real-time system conditions. Run-time reconfiguration mayalso be initiated by, for example, user command line inputs, user GUIinputs, and the state or an action of the programmable logic device 202itself.

At step 318, based on the information from step 316, the applicationprogram 204 selects the logic cores, which define the new circuit to beimplemented. Steps 320, 322, 324, and 326 are similar to steps 304, 306,308, and 310, respectively. However, the steps differ in that they canbe performed while the example device 202 is providing its existingfunction.

It will be appreciated that downloading the bitstream as set forth instep 326 can involve either a partial reconfiguration or fullreconfiguration of the programmable logic device 202. For example, theXC4000 series FPGAs from XILINX support only full reconfiguration,whereas the XC6200 FPGA and future devices available from XILINX supportpartial reconfiguration. If a small modification is being made to anexisting bitstream, it is not necessary to rewrite the entire bitstream.Thus, the term “bitstream” is intended to encompass sequences ofprogramming bits for both partial and full reconfiguration.

The discussion that follows is directed to implementing on an exampleFPGA an example counter and adder, and coupling the two logic cores. Thecoupling of the counter to the adder is accomplished using an examplerouter core function in the core library 206.

A router core is generally used as follows. First the two logic cores tobe connected are instantiated or “defined” using the appropriategenerators from the core library 206. Then the programming bitsinstantiating these logic cores in their respective locations in theprogramming bitstream 210 are generated and stored using applicationprogram interface 207 and bit-level interface 208. Once the selectedlogic cores are instantiated, a router core is instantiated using thecore library 206, and the associated programming bits are stored, againusing application program interface 207 and bit-level interface 208.

The following code fragment, set off in italics, illustrates exampleinstructions of a user application 204. The code includes instructionsthat build a 16-bit counter and a 16-bit adder that adds the value 7 toits input. The router core in the example connects the configurablelogic block (CLB) YQ outputs of the counter to the F1 LUT inputs of theadder. Because the router core occupies no CLBs, it is treated as havingno width, and is “set( )” to the same location as the constant adder.The “JBits” nomenclature corresponds to functions provided by thebit-level interface 208, and the term “stitcher” refers to generation ofthe router core.

/** © 1998 XILINX, INC. **/ /* set up the bit-level interface */ jb =new JBits(deviceType); /* instantiate a 16-bit counter core atCLB(10,10) */ Counter counter = new Counter(16,5); counter.set(jb, 10,10); /* instantiate a 16-bit +7 adder core at CLB(10,11) */ ConstAdderconstAdder = new ConstAdder(16, 7); constAdder.set(jb, 10, 11); /*stitch the counter and adder together */ Stitcher stitcher = newStitcher(Stitcher.F1_IN, Stitcher.YQ_OUT, 16); stitcher.set(jb, 10, 11);

FIG. 4 is a schematic that illustrates a portion of an example FPGAconfigured in accordance with the example code fragment set forth above.The illustrated portion of the FPGA includes CLBs 402 a-d at column 10,rows 10-13 and CLBs 402 e-h at column 11 rows 10-13. CLBs 402 a-d areconfigured to implement the counter, CLBs 402 e-h are configured toimplement the adder, and interconnect switches 404 a-d are configuredfor coupling the counter CLBs to the adder CLBs. The router connectionsare, for example, direct connect signal lines for coupling adjacent CLBsin a XC4000 series FPGA. While direct connect switches are illustrated,it will be appreciated that more complex router cores could beimplemented to make use of the aforementioned single, double, quad,long, and global signal lines, as well as programmable signal lines thatare available in programmable logic devices from other manufactures. Itwill also be appreciated that different programmable logic devices fromvendors other than XILINX could also make use of the present invention.As long as the architecture includes an array having blocks of logic anda distributed routing architecture, both of which are programmable, theinvention is applicable. The invention is applicable to hierarchicalarchitectures having blocks of blocks of logic.

Three code fragments are provided below to illustrate example Javaclasses provided by the core library 206. The first class illustrates acounter core, the second class illustrates a router core, and the thirdclass illustrates a generic template that can be used as the startingpoint for creating additional objects in the core library 206. Fromthese three classes, those skilled in the art will recognize how toimplement additional cores for various functions and provide access tothe architectural features of a programmable logic device 202.

The following class defines a counter. The counter implementation shownbelow consumes a single CLB per stage. It will be appreciated thatalternative counter cores could be implemented which do not consume asingle CLB per stage. Comments are interspersed with the code to explainthe functionality.

/** © 1998 XILINX, INC. **/ public class Counter extends Core { /**Local data */ private int size = 0; private int init = 0; /** ** Thisconstructor sets up the counter core object. The ** size parameterdefines the number of stages in ** the counter. The initial value of thecounter is set ** to a default of zero. ** ** @param _size The number ofstages in the counter ** */ public Counter(int _size) { /* Defaultinitial state to zero */ init = 0; size = _size; /* Allocate the counterstate object */ state = new State(_size); /* Save the CLB width andheight */ clbHeight = _size; clbWidth = 1; /* Give the counter a defaultname */ name = “Counter”; } /* end Counter() */ /** ** This constructorsets up the counter core object. The ** size parameter defines thenumber of stages in ** the counter. The init parameter gives the **initial value of the counter. ** ** @param _size The number of stages inthe counter ** ** @param _init The initial value of the counter. ** */public Counter(int _size, int _init) { init = _init; size = _size; /*Allocate the counter state symbol */ state = new State(_size); /* Savethe CLB width and height */ clbHeight = _size; clbWidth = 1; /* Give thecounter a default name */ name = “Counter”; } /* end counter() */ /** **See the set() function in the Core object ** for a description of thisfunction. ** ** @see Core ** */ public int set(JBits jb, int _clbRow,int _clbColumn) { int result; int bit; int i; int row; int col; /* F2{circumflex over ( )} F3 */ int XOR[] = {0,1,1,0, 0,1,1,0, 0,1,1,0,0,1,1,0); /* FI & F2 */ int AND[] = {0,0,0,1, 0,0,0,1, 0,0,0,1,0,0,0,1); /* Be sure we haven't written already */ if (written == true)return (−1); /* Save the CLB row and column */ clbRow = _clbRow;clbColumn = _clbColumn; /* The column does not change */ col =clbColumn; bit = 0; for (row=clbRow; row<(clbRow+size); row++) { /* SetF LUT */ if (row == clbRow) { result = jb.setF(row, col, LUT.INVERTER1);result = jb.setG(row, col, LUT.BUFFER1); } else { result = jb.setF(row,col, XOR); result = jb.setG(row, col, AND); } /* Set Y output to outputof G LUT */ result = jb.set(row, col, Y.OUT, Y.G); /* Set flip flopinputs (both from F LUT) */ result = jb.set(row, col, YFF.D, YFF.F);result = jb.set(row, col, XFF.D, XFF.F); /* Set F2 and G2 inputs to Youtput of CLB below (via single wire) */ result = jb.set(row, col,Y.HORIZ_SINGLE1, Y.ON); result = jb.set(row, col, F2.F2,F2.HORIZ_SINGLE1); result = jb.set(row, col, G2.G2, G2.HORIZ_SINGLE1);/* Set F1 and G1 inputs to XQ output of CLB (via single wire) */ result= jb.set(row, col, XQ.VERT_SINGLE1, XQ.ON); result = jb.set(row, col,F1.F1, F1.VERT_SINGLE1); result = jb.set(row, col, G1.G1,G1.VERT_SINGLE1); /* Set the inital state */ if (((init >> bit) & 0x01)== 0) { result = jb.set(row, col, YFF.SR_SELECT, YFF.RESET); result =jb.set(row, col, XFF.SR_SELECT, XFF.RESET); } else { result =jb.set(row, col, YFF.SR_SELECT, YFF.SET); result = jb.set(row, col,XFF.SR_SELECT, XFF.SET); } /* Set flip flop clocks (shared) */ result =jb.set(row, col, Clock.CLOCK, Clock.CLOCK4); /* Enable flip flop clocks*/ result = jb.set(row, col, YFF.DISABLE_CLOCK, YFF.OFF); result =jb.set(row, col, XFF.DISABLE_CLOCK, XFF.OFF); /* Set flip flops to latchmode */ result = jb.set(row, col, YFF.LATCH, YFF.OFF); result =jb.set(row, col, XFF.LATCH, XFF.OFF); /* Set up state vector (alloutputs use XQ) */ state.setBitEntry(bit, row, col, State.XQ); bit++; }/* end for(col) */ /* Set the written flag */ written = true; return(0); } /* end set() */ }; /* end class Counter */

The following code fragment sets forth an example Java class forimplementing a router core that can be used to connect two adjacentlogic cores, or other groups of adjacent CLBs. A left-to-right data flowis assumed. However, it will be appreciated that this class could beextended to support data flow in other directions. A stride bit of 1 isassumed, which means that each CLB row carries one bit of the data path.

Because of the geometry of the example supported devices, namely, theXC4000 family of devices, the only valid output resources are Y and YQ.The valid inputs are F1, C1, and G1. Selecting an input, an output and asize causes each selected output to be connected to a correspondingselected input.

This router core object has a width of zero because it consumes no CLBlogic. This core uses the direct connect signal lines between CLBs. Notethat since the present method replaces a more elaborate automaticrouting algorithm, it is left to the user to ensure that these routingresources are not in use. Also note that the “set( )” function should beapplied to the desired core input because, since the input row andcolumn is specified in the set( ) function, the routing is more closelyassociated with inputs than outputs.

/** © 1998 XILINX, INC. **/ public class Stitcher extends Core { /** TheCLB input resources **/ public final static int G1_IN = 0; public finalstatic int C1_IN = 1; public final static int F1_IN = 2; /** The CLBoutput resources **/ public final static int Y_OUT = 3; public finalstatic int YQ_OUT = 4; /** Local data **/ private int input = −1;private int output = −1; private int size = 0; /** ** This constructorsets up the Stitcher core object. ** ** @param _input This is the CLBinput signal to which **   outputs from the CLB to the left are to be **  connected. **   Valid values are G1, C1 and Fl. ** ** @param _outputThis is the CLB output signal to which **   the CLB inputs are to beconnected. Note that **   these output signals are from the CLB to the**   left. Valid Values are X, XQ, Y and YQ. ** ** @param _size Thenumber of stages in the counter ** */ public Stitcher(int _input, int_output, int _size) { /* Save local variables */ input = _input; output= _output; size = _size; /* Save the CLB width and height */ clbHeight =_size; clbWidth = 0; /* Always zero */ /* Give the router a default name*/ name = “Stitcher”; } /* end Stitcher() */ /** ** See the set()function in the Core object ** for a description of this function. ** **@see Core ** */ public int set(JBits jb, int _clbRow, int _clbColumn) {int result; int i; int row; int col; /* Be sure we haven't writtenalready */ if (written == true) return (−1); /* Save the CLB row andcolumn */ clbRow = _clbRow; clbColumn = _clbColumn; /* The column doesnot change */ col = clbColumn; for (row=clbRow; row<(clbRow+size);row++) { /* There are 6 possible settings */ /* (all combinations ofinputs and outputs) */ if ((output == YQ_OUT) && (input == G1_IN)) {result = jb.set(row, col, G1.G1, G1.OFF); result = jb.set(row, col,YQ.G1, YQ.ON); } else if ((output == YQ_OUT) && (input == C1_IN)) {result = jb.set(row, col, C1.C1, C1.OFF); result = jb.set(row, col,YQ.C1, YQ.ON); } else if ((output == YQ_OUT) && (input == F1_IN)) {result = jb.set(row, col, F1.F1, F1.OFF); result = jb.set(row, col,YQ.F1, YQ.ON); } else if ((output == Y_OUT) && (input == G1_IN)) {result = jb.set(row, col, G1.G1, G1.OFF); result = jb.set(row, col,Y.G1, Y.ON); } else if ((output == Y_OUT) && (input == C1_IN)) { result= jb.set(row, col, C1.C1, C1.OFF); result jb.set(row, col, Y.C1, Y.ON);} else if ((output == Y_OUT) && (input == F1_IN)) { result = jb.set(row,col, F1.F1, F1.OFF); result = jb.set(row, col, Y.F1, Y.ON); } elsereturn (−1); } /* end for(col) */ /* Set the written flag */ written =true; return (0); } /* end set() */ } /* end class Stitcher */

The following code fragment serves as a template for dynamicallyparameterizable, relocatable cores in the core library 206. This core isimplemented as an abstract Java class and is not functional by itself.It can be used as a template to create additional core objects in thelibrary 206.

Because this is an abstract class, no constructor is supplied, however,each implemented core object must provide a constructor. The constructorsets the local variables that define the ClbWidth, ClbHeight, the Name,the State symbol, and any other data that may be required by the core.Note that no actual circuit implementation is done by the constructor;only local parameters are defined. All circuit construction should takeplace in the set( ) function, which writes configuration informationdirectly into the bitstream.

Each core in the library is preferably a separate object that can onlybe set( ) once. While the constructor and the set( ) function could bemerged, the separation is believed to produce better core objects. Coredefinition is separated from core implementation, and correct usage ofparameters is promoted by this structure.

/** © 1998 XILINX, INC. **/ public abstract class Core { /** Local data**/ /* The size of the Core */ protected int clbWidth = 0; protected intclbHeight = 0; /* The Core origin location */ protected int clbRow = −1;protected int clbColumn = −1; /* The Core state */ protected State state= null; /* The Core name indentifier */ protected String name =“Undefined”; /* The written flag (so each object is only set() once) */protected boolean written = false; /** ** ** This function does nearlyall of the work in building a ** JBits Core. It configures all CLBs andperforms all ** routing. This definition of the core circuit is done **at run-time and data is written directly into the ** JBitsconfiguration. This function uses any local ** data supplied to the Coreconstructor as parameters. ** Note that the amount of parameterizationpossibie in a ** circuit is not limited by this approach. Any number or** range of parameters may be supported in this manner. ** Note that itis also the responsibility of this function ** to: ** ** Return an errorif the written flag is true ** Store the row and column origin of thecore **  for future reference ** Construct the State object ** Configurethe Core into a JBits object ** Set the written flag to true. ** ** **@param jb This is the JBits object representing **   the selected deviceconfiguration. ** ** @param clbRow This is the CLB row at which tolocate **   the Core. By convention, the origin is in the **   lowerleft corner of the Core. ** ** @param clbColumn This is the CLB columnat which to **   locate the Core. By convention, the origin is **   inthe lower left corner of the Core. ** ** @return This function returns a0 on success and a **   negative error code on failure. */ publicabstract int set(JBits jb, int _clbRow, int _clbColumn); /* **Non-abstract functions ** */ /**** This function returns the name of thecore. This name is a text ** String with no specific meaning. It is usedprimarily for ** debugging purposes. ** ** @return This function returnsthe name of the Core. ** */ public String getName() { return (name); }/* end getName() */ /** ** This function returns the width of the corein CLBs. ** ** @return This function returns the width of the core in **CLBs. ** ** @see getClbHeight ** /* public int getClbWidth() { return(clbWidth); } /* end getclbWidth() */ /** ** This function returns theheight of the Core in CLBs. ** ** @return This function returns theheight of the Core in ** CLBs. ** ** @see getClbWidth ** */ public intgetClbHeight() { return (clbHeight); } /* end getclbHeight() */ /** **This function returns the row in the CLB array which ** contains theorigin of the Core. By convention the ** origin of the core is in thelower left corner. ** ** @return This function returns row origin of theCore. ** ** @see getClbColumn ** */ public int getClbRow() { return(clbRow); } /* end getClbRow() */ /** ** This function returns thecolumn in the CLB array which ** contains the origin of the Core. Byconvention the ** origin of the core is in the lower left corner. ** **@return This function returns column origin of the ** Core. ** ** @seegetClbRow ** */ public int getClbColumn() { return (clbColumn); } /* endgetClbColumn() */ /** ** This function returns the state of the core asdefined ** in the state object. The state is read back from the **configuration data in the JBits object <em>jb</em>. ** ** @param jb TheJBits object containing the ** configuration data. ** ** @return Thisfunction returns state of the Core. ** /* public long getState(JBits jb){ return (state.get(jb)); } /* end getState() */ }; /* end class Core */

Accordingly, the present invention provides, among other aspects, amethod and system for configuration and run-time reconfiguration ofprogrammable logic devices. Other aspects and embodiments of the presentinvention will be apparent to those skilled in the art fromconsideration of the specification and practice of the inventiondisclosed herein. It is intended that the specification and illustratedembodiments be considered as examples only, with a true scope and spiritof the invention being indicated by the following claims.

What is claimed is:
 1. A method for configuration of a programmablelogic device that is coupled to a processor using a library thatcomprises logic core generators and one or more router core generators,each of the logic and router core generators including code that isexecutable and embodies design information, comprising the steps of:executing a program on the processor, the program including instructionsthat reference selected ones of the logic core generators for functionsto be provided by the programmable logic device; generating by one ormore of the logic core generators in response to the program, logic coredefinitions that define at least two logic cores; generating by therouter generators in response to the program, at least one router coredefinition that defines a coupling of the logic cores in theprogrammable logic device; generating programming bits from the logiccore definitions and router core definition in response to the program;and loading the programmable logic device with the programming bits inresponse to the program.
 2. The method of claim 1, further comprisingspecifying placement information for the logic cores to the logic coregenerators.
 3. The method of claim 2, wherein the placement informationincludes a row and a column in a matrix of configurable units.
 4. Themethod of claim 2, further comprising specifying connections for inputresources of a first one of the logic core generators to outputresources of a second one of the logic core generators.
 5. The method ofclaim 1, further comprising programming the processor with instructionsof a selected language to provide a plurality of functions, whereinconfiguration of the programmable logic device with the library ofgenerators is one of the selected functions.
 6. The method of claim 5,wherein the processor is further programmed for: monitoring selectedoperating conditions; generating new programming bits in response toselected operating conditions; and loading the programmable logic devicewith the new programming bits.
 7. The method of claim 1, wherein thelogic and routing generators are Java objects.
 8. The method of claim 1,wherein the programmable logic device is a FPGA.
 9. The method of claim8, wherein the router core definition defines a coupling using a signalline selected form the group of direct, single, double, quad, long, andglobal signal lines.
 10. A system for run-time reconfiguration of aprogrammable logic device, comprising: a library of logic coregenerators and router core generators accessible for initiation by theapplication program and executable on the processor, each of the logicand router core generators including code that is executable and thatembodies design information; a processor hosting a run-timereconfiguration program, the program including instructions thatreference selected ones of the logic and router core generators; aprogramming bit generator accessible for initiation by the run-timereconfiguration program and arranged for generation of programming bitsin response to output of the logic core and router core generators; aprogrammable logic device coupled to the processor and configurable withthe programming bits.
 11. The system of claim 10, further comprisingmeans for placement of the logic cores in the programmable logic device.12. The system of claim 11, further comprising means for coupling inputresources of a first one of the logic core generators to outputresources of a second one of the logic core generators.
 13. The systemof claim 10, wherein the program includes instructions of a selectedlanguage arranged to provide a plurality of functions, whereinconfiguration of the programmable logic device with the library ofgenerators is one of the selected functions.
 14. The system of claim 13,wherein the program includes instructions arranged to: monitor selectedoperating conditions; generate new programming bits in response toselected operating conditions; and load the programmable logic devicewith the new programming bits.
 15. The system of claim 10, wherein thelogic and router core generators are Java objects.
 16. The system ofclaim 10, wherein the programmable logic device is an FPGA.
 17. Anapparatus for configuration of a programmable logic device that iscoupled to a processor, comprising: means for selecting functions to beprovided by the programmable logic device with program instructionreferences to selected logic core generators and router core generatorsin a library of core generators, each of the logic and router coregenerators including code that is executable and that embodies designinformation; means for generating logic core definitions by the selectedlogic core generators; means for generating by the selected router coregenerators router core definitions that define couplings between thelogic cores in the programmable logic device; means for generatingprogramming bits from the logic core definitions and router coredefinition; and means for loading the programmable logic device with theprogramming bits.
 18. A method of configuring a field programmable gatearray (FPGA), the FPGA being connected to a host processor forconfiguration thereby, comprising the steps of: a) programming the hostprocessor with instructions in a high level programming language; b)instantiating first and second logic elements from a library of elementscompatible with the high level programming language, the first andsecond logic elements defining first and second functions, respectively;c) instantiating a routing element from the library of elementscompatible with the high level programming language, the routing elementdefining a route between the first and second logic elements; d)providing a compiler for the high level programming language to the hostprocessor for generating executable code in response to the programmedinstructions and the instantiated library elements, the executable codeincluding compiled placement and routing information; e) configuring theFPGA from the host processor in response to the executable code.
 19. Themethod of claim 18, wherein the FPGA is used for dynamicallyreconfigurable computing.
 20. The method of claim 19, wherein the logicelements and routing element are parameterizable.